The APB Interconnect core provides solution to connect multiple APB masters to a single APB slave. The APB Interconnect core supports two arbitration modes to determine the grant access of the masters. The APB Interconnect core operates based on the Advanced Microcontroller Bus Architecture (AMBA) 3 Advanced Peripheral Bus (APB) protocol specifications version 1.0.

APB Interconnect Core Block Diagram

Features

The APB Interconnect core includes the following features:

• Compliant with AMBA 3 APB Protocol specifications
• Data width up to 32 bits [1, 2, …, 32]
• Address width up to 32 bits [1, 2, …, 32]
• Fixed-Priority and Round-Robin arbitration modes
• Supports arbitration up to 32 masters to a single slave
• Optional pipeline registers to optimize latency or/and performance
• Include indicators on which master is being granted the request