The DDR Hard Memory Controller-Calibration core helps you optimize timing and calibrate the Trion® DDR controller using write leveling, read leveling, and gate training. The core supports an automated calibration mode as well as calibration on demand, depending on your configuration. The core consists of an automation state machine, a calibration state machine, and an I²C master.

DDR Hard Memory Controller-Calibration Block Diagram

Features

• Automatically performs leveling calibration for the DDR DRAM interface and external memory module
• Supports write leveling, read leveling, and gate training calibration
• Programmable calibration steps and sequence using ROM memory files
• Verilog RTL and simulation testbench
• Includes an example design targeting the T120 BGA324 development board
• Supports Trion FPGAs with DDR blocks