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DDR Hard Memory Controller-Reset

Some Trion® FPGAs have a hardened DDR controller block. Resetting this DDR block involves more than a simple reset; you also need to reconfigure the block and re-initialize the memory. The DDR Hard Memory Controller-Reset core manages this process for you. The DDR Hard Memory Controller-Reset core resets and re-initializes the Trion FPGA's DDR interface as well as the DDR module(s). You use this soft logic reset when you want to reset the DDR system while the TrionĀ® FPGA is in user mode.

DDR Hard Memory Controller-Reset Core Block Diagram

DDR Hard Memory Controller-Reset Block Diagram

Features

  • Resets the DDR controller and PHY and external memory
  • Re-initializes the external memory
  • Verilog RTL and simulation testbench
  • Supports Trion FPGAs with DDR blocks



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