The DDR3 Soft Controller Core is a memory controller core that interfaces with industry standard DDR SDRAM modules. The core also handles the timing parameters, priority, and other memory operations with DDR3 modules.

DDR3 Soft Controller Block Diagram (Native)

DDR3 Soft Controller Block Diagram (AXI4)

Features

• Mode register set customization
• Fully parameterized to be compatible with any DDR3 device
• Supports x8/x16 DRAM memory
• Data rate up to 800 MT/s (x16 devices)
• Supports burst length of 8
• Native and AXI4 interface
• DQ input auto-calibration
• Supports:
  • 1 rank support
  • Bank interleaving
  • Half-Rate
  • Random access within the same row
• Verilog HDL RTL and simulation testbench
• Supports all Titanium FPGAs