The Divider core divides a numerator input value by a denominator input value to produce a quotient and a remainder.

Divider Block Diagram

Features

• Supports a data width of 2 to 64 bits
• Supports signed and unsigned data representation format for both the numerator and denominator
• Supports optional asynchronous clear and clock enable ports
• Verilog HDL RTL and simulation testbench
• Includes an example design targeting the Trion® T20 BGA256 Development Board and Titanium Ti60 F225 Development Board
• Supports all Trion and Titanium FPGAs