The PLL Dynamic Reconfiguration core allows users to change the PLL settings on an Efinix FPGA, without changing the settings in the Interface Designer, re-compiling, and re-generating the bitstream file. This IP core provides an efficient way to change the PLL settings on the fly after initial boot-up, without having to re-configure the FPGA.

PLL Dynamic Reconfiguration Core Block Diagram

Features

The PLL Dynamic Reconfiguration core includes the following features:

• Allow maximum 85 PLL settings to be stored and reconfigure the PLL
• Allows the FPGA to revert to the original PLL settings in the bitstream file.
• Single_CFG and multi_CFG mode.

Note: The original PLL settings are also known as Peripheral Configuration Register (PCR) settings.