Jade RISC-V SoC
Note: the Jade SoC is end of life in the Efinity software v2022.1.226. This SoC is replaced by the Sapphire SoC.
The Jade SoC incorporates a 32-bit RISC-V processor, 4 KB instruction cache, 4 KB data cache, 32 KB of on-chip RAM, and a variety of peripherals (including 1 APB3 slave peripherals).
Jade SoC Block Diagram
Features
- VexRiscv processor with 5 pipeline stages (fetch, decode, execute, memory, and write
back), interrupts and exception handling with machine mode
- 4 KB data cache
- 4 KB instruction cache
- 10 - 350 MHz system clock frequency
- 32 KB on-chip RAM with boot loader for SPI flash
- APB3 peripherals:
- 16 GPIOs
- 2 I2C masters and slaves
- Machine timer
- PLIC
- 2 SPI flash masters with a maximum clock frequency of 25 MHz
- 1 UART with 115,200 baud rate
- 1 slave user peripheral
FPGA Support
The Jade SoC supports all Titanium FPGAs and T20, T35, T55, T85, and T120 Trion® FPGAs.
Titanium Resource Utilization and Performance
| FPGA | Logic/Adders | FlipFlops | Memory Blocks | DSP48 Blocks | fMAX (MHz) | Language | Efinity Version |
|---|---|---|---|---|---|---|---|
| Ti60 F225 C3 (min) | 4,892 | 2,885 | 26 | 4 | 187 | Verilog HDL | 2021.1 |
Trion Resource Utilization and Performance
| FPGA | Logic Utilization (LUTs) | Memory Blocks | fMAX (MHz) | Language | Efinity Version |
|---|---|---|---|---|---|
| T20 BGA256 C4 | 6,193 | 37 | 118 | Verilog HDL | 2021.1 |