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High-Performance Sapphire RISC-V SoC

The High-Performance Sapphire SoC is a hardened RISC-V CPU block consisting of quad cores that run up to 1 GHz. It is highly coupled with FPGA user logic to realize the application; thus, it provides rich sets of I/Os that communicate with the FPGA fabric, e.g., AXI interface, custom instructions interface, and user interrupts. The high-performance Sapphire SoC also supports a variety of I/O peripheral controllers. You can choose which peripheral you want by configuring the SoC in the IP Manager. This SoC has better overall performance than the soft Sapphire SoC.

The hardened RISC-V CPU block, also known as HRB, incorporates quad 32-bits RISC-V cores which supports:

  • Integer (i)
  • Multiply (m)
  • Atomic (a)
  • Compressed (c)
  • Single and double precision floating-point (fd) instruction extensions
  • 4-ways 16 kB data and instruction caches
  • 16 kB of on-chip RAM
  • 2 user timers
  • 24-pin user interrupts

Additionally, the IP Manager supports the generation of soft I/O controllers: up to 3 SPI and I2C controllers, 2 sets of GPIO up to 32 pins each, a watch dog timer, 3 sets of APB3 interface and connect them to HRB’s AXI interface automatically, together with other required blocks like PLLs, LPDDR4 and I/O pins assignment.

Documentation

Sapphire High-Performance Risc-V SoC Data Sheet

Sapphire High-Performance Risc-V SoC Hardware and Software User Guide

High Performance Sapphire SoC Block Diagram

Features

  • 4 VexRiscv processor(s) with 6 pipeline stages (fetch, injector, decode, execute, memory, and write back), interrupts, and exception handling with machine mode and supervisor mode.
  • Up to 1 GHz system clock frequency
  • 16 KB on-chip RAM
  • Memory controller for LPDDR4x
    • Supports memory module size of 3.7 GB
    • 1 full-duplex 512-bits AXI4 interface to communicate with the external memory
    • User-configurable external memory bus frequency
  • 1 AXI master channel for user logic, data width of 128-bits
  • 1 AXI slave channel to user logic
  • Each core includes:
    • 4-way 16 KB data and instruction caches
    • Floating point unit (FPU)
    • Linux memory management unit (MMU)
    • Custom instruction interface with 1,024 IDs to perform various functions
  • Supports RISC-V extensions such as integer, multiply, atomic, compressed, single, and double-digit floating point.
  • JTAG debug module with 8 hardware breakpoints
  • Peripherals:
    • 2 user timers
    • 24 user interrupts

FPGA Support

The Sapphire SoC supports all Titanium Ti375FPGAs and selected Topaz FPGAs like Tz75, Tz100, Tz200, and Tz325.



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