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Sapphire RISC-V SoC

The Sapphire SoC is a cached soft RISC-V SoC that optionally includes a memory controller interface. The Sapphire SoC supports a variety of peripherals. You can choose which peripherals you want by configuring the SoC in the IP Manager. This core is similar to the open-source SaxonSOC, but it has been optimized for Trion® and Titanium FPGAs.

The Sapphire SoC incorporates a 32-bit RISC-V processor, 1 - 32 KB instruction cache, 1 - 32 KB data cache, 4 - 512 KB of on-chip RAM, and a variety of peripherals (including 1 - 5 APB3 slave peripherals and 1 AXI slave). You can configure the operating frequency from 10 - 400 MHz (the actual performance is limited by the design's fMAX). The SoC includes 1 - 3 I2C peripherals and 1 - 3 SPI masters.

The default configuration has a 128-bit half-duplex AXI bus to communicate with the Efinix DDR controller or HyperRAM controller.

  • DDR controller—This core uses the Trion FPGAs hard DDR DRAM interface to reset an external DRAM module (resets and re-initializes the Trion FPGA's DDR interface as well as the DDR module(s)).
  • HyperRAM controller—This core controls HyperRAM memory modules. You can customize the SoC using the IP Manager in the Efinity  software.

Documentation

Sapphire Risc-V SoC Data Sheet

Sapphire Risc-V SoC Hardware and Software User Guide

Sapphire SoC Block Diagram

Sapphire SoC Multi-Core Block Diagram

Features

  • 1 - 4 (user selectable) VexRiscv processor(s) with 6 pipeline stages (fetch, injector, decode, execute, memory, and write back), interrupts and exception handling with machine mode
  • 20 - 400 MHz system clock frequency
  • 1 - 512 KB on-chip RAM with boot loader for SPI flash
  • Memory controller for DDR3, LPDDR4x or HyperRAM memories
    • Supports memory module sizes from 4 MB to 3.5 GB
    • User-configurable external memory bus frequency
    • 1 half duplex AXI3 interface or 1 full duplex AXI4 interface (up to 512-bits) to communicate with the external memory
    • 400 MHz DDR3 clock frequency, 800 Mbps
    • 1089 MHz LPDDR4x clock frequency, 2178 Mbps
    • 250 MHz HyperRAM clock frequency, 500 Mbps
  • Up to 2 AXI master channels for user logic, data widths from 32 to 512
  • 1 AXI slave channel to user logic
  • Includes an optional multi-way instruction and Data Cache
  • Includes a floating point unit (FPU)
  • Includes an optional Linux memory management unit (MMU)
  • Includes an optional custom instruction interface with 1,024 IDs to perform various functions
  • Supports optional RISC-V extensions such as atomic and compressed
  • APB3 peripherals:
    • Up to 32 GPIOs
    • Up to 3 I2C masters
    • Clint timer
    • Platform-level interrupt controller (PLIC)
    • Up to 3 SPI masters
    • Up to 3 user timers
    • Up to 3 UARTs with 115,200 baud rate
    • Up to 5 slave user peripherals
    • Up to 8 user interrupts

FPGA Support

The Sapphire SoC supports all Trion® FPGAs (except the T4) and all Titanium FPGAs, however, you may only be able to use some of the features in certain devices. For example, the DDR controller only works with FPGAs that have a hardened DDR controller block.

Titanium Resource Utilization and Performance

The Sapphire is configurable. These tables show the resource usage for various configurations.

Table 1. Cacheless SoC with External Memory (Standard Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP48 Blocks fMAX (MHz) Efinity Version
Ti60 F225 C4 (typical) 7,157 7,585 44 4 360 2023.2
Ti60 F225 C4 (custom instruction) 7,405 7,623 44 4 354 2023.2
Table 2. Cacheless SoC without External Memory (Standard Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP48 Blocks fMAX (MHz) Efinity Version
Ti60 F225 C4 (typical) 4,519 3,067 12 4 350 2023.2
Ti60 F225 C4 (custom instruction) 4,541 3,104 12 4 371 2023.2
Table 3. Cached SoC with External Memory (Standard Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP48 Blocks fMAX (MHz) Efinity Version
Ti60 F225 C4 (typical) 7,773 8,024 56 4 393 2023.2
Ti60 F225 C4 (custom instruction) 7,822 8,065 56 4 382 2023.2
Ti60 F225 C4 (FPU) 14,428 12,148 77 13 285 2023.2
Ti60 F225 C4 (2 cores) 14,777 13,077 103 8 322 2023.2
Ti60 F225 C4 (3 cores) 19,127 15,410 127 12 317 2023.2
Ti60 F225 C4 (4 cores) 23,389 17,673 150 16 317 2023.2
Table 4. Cached SoC without External Memory (Standard Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP48 Blocks fMAX (MHz) Efinity Version
Ti60 F225 C4 (typical) 5,051 3,483 24 4 390 2023.2
Ti60 F225 C4 (custom instruction) 5,030 3,525 24 4 384 2023.2
Ti60 F225 C4 (FPU) 11,696 7,621 44 13 288 2023.2
Ti60 F225 C4 (2 cores) 11,871 8,234 62 8 321 2023.2
Ti60 F225 C4 (3 cores) 15,894 10,555 87 12 325 2023.2
Ti60 F225 C4 (4 cores) 19,967 12,806 110 16 306 2023.2
Table 5. Cacheless SoC (Lite Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP48 Blocks fMAX (MHz) Efinity Version
Ti60 F225 C4 (external memory) 3,316 2,734 14 0 363 2023.2
Ti60 F225 C4 (internal memory) 2,729 1,909 24 0 385 2023.2
Table 6. Cached SoC (Lite Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP48 Blocks fMAX (MHz) Efinity Version
Ti60 F225 C4 (external memory) 3,659 2,923 26 0 329 2023.2
Ti60 F225 C4 (internal memory) 3,285 2,087 36 0 381 2023.2

Trion Resource Utilization and Performance

The Sapphire is configurable. These tables show the resource usage for various configurations.

Table 7. Cacheless SoC with External Memory (Standard Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
T120 F324 (typical) 7,230 7,731 48 4 106 2023.2
T120 F324 (custom instruction) 7,306 7,770 48 4 105 2023.2
Table 8. Cacheless SoC without External Memory (Standard Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
T120 F324 (typical) 4,588 3,208 16 4 110 2023.2
T120 F324 (custom instruction) 4,557 3,251 16 4 99 2023.2
Table 9. Cached SoC with External Memory (Standard Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
T120 F324 (typical) 7,915 8,175 67 4 116 2023.2
T120 F324 (custom instruction) 8,017 8,217 67 4 105 2023.2
T120 F324 (FPU) 14,842 12,519 80 13 86 2023.2
T120 F324 (2 cores) 14,861 13,352 109 8 87 2023.2
T120 F324 (3 cores) 19,444 15,817 136 12 90 2023.2
T120 F324 (4 cores) 23,093 18,216 162 16 89 2023.2
Table 10. Cached SoC without External Memory (Standard Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
T120 F324 (typical) 5,051 3,626 35 4 113 2023.2
T120 F324 (custom instruction) 5,063 3,672 35 4 103 2023.2
T120 F324 (FPU) 12,377 8,034 47 13 83 2023.2
T120 F324 (2 cores) 11,992 8,507 68 8 89 2023.2
T120 F324 (3 cores) 16,461 10,960 96 12 91 2023.2
T120 F324 (4 cores) 20,630 13,343 122 16 94 2023.2
Table 11. Cacheless SoC (Lite Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
T120 F324 (external memory) 3,386 2,748 18 0 103 2023.2
T120 F324 (internal memory) 2,726 1,923 40 0 111 2023.2
Table 12. Cached SoC (Lite Option)
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
T120 F324 (external memory) 4,035 2,970 37 0 109 2023.2
T120 F324 (internal memory) 3,330 2,135 59 0 113 2023.2


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