The integer square root core calculates the integer square root of an input value. The relationship between the integer I, square root result Q, and remainder R is given by these equations:

• I = Q² + R, where I, Q, and R are integers ≥ 0
• Q is the largest possible value

Integer Square Root Core Block Diagram

Features

• Integer square root function
  • Returns an integer result and any remainder
  • Parameterized input, result, and remainder widths
• User-defined delay for output result
• User-selectable modes:
  • Continuous—Pipelined for high speed; supports multiple calculations and uses more resources
  • Single—Uses fewer resources; you can specify the number of calculation units
• Verilog RTL and simulation testbench
• Includes an example design targeting the Trion® T20 BGA256 Development Board and Titanium Ti60 F225 Development Board
• Supports all Trion and Titanium FPGAs