The Trion DDR Calibration and Debug IP core helps you calibrate and reset the Trion DDR controller using CA training, write leveling, read leveling, gate training, and reset sequencing (memory initialization).

Trion DDR Calibration and Debug IP Block Diagram

Features

• Automatically performs leveling calibration for the DDR DRAM interface and external memory module
• Supports CA training, write leveling, read leveling, reset (memory initialization), and gate training calibration
• x16 and x32 DQ widths
• Verilog RTL
• Includes an example design targeting the Trion T120 BGA324 and T120F576 Development Board