The Trion PLL Auto-Rese core improves the PLL functionality by efficiently resetting the PLLs. Trion FPGAs have phase-locked loops (PLLs) situated at the corners of the FPGA, which are used to generate clock signals for your design. You can use PLLs to compensate for clock skew or delay through external or internal feedback, thus meeting the timing requirements for advanced applications.

Trion PLL Auto-Reset Core Block Diagram

Features

The Trion PLL Auto-Reset core includes the following features:

• Checking on the PLL lock status after the reset is triggered
• Reset pulse triggering after time-out