The Triple Speed Ethernet MAC transmits and receives data between a host processor and an Ethernet network. The Ethernet MAC's primary function is to ensure the transmission of data over the Ethernet meets the media access rules specified in the 802.3-2008 IEEE Std.

Triple Speed Ethernet MAC Block Diagram

Features

• Complies to the IEEE Std. 802.3-2008 specification
• Supports 1000 Mbps, 100 Mbps, and 10 Mbps with full duplex transfer mode
• Management data I/O (MDIO) for PHY device management
• Supports VLAN frame and jumbo frame
• Includes statistic counter, address filtering, TX interpacket gap (IPG), and pause frame flow control
• Supports internal FIFO and error-correction code (ECC) protection
• Programmable source and destination MAC addresses
• RGMII, RMII, GMII, and MII PHY interfaces
• 8-bit, 16-bit, and 32-bit AXI4-Stream user interface for packet transfer
• AXI4-Lite user interface for MAC register setting
• Includes an example design targeting:
  • Trion® T120 BGA324 Development Board
  • Titanium Ti60 F225 Development Board