The Universal Asynchronous Receiver/Transmitter (UART) core converts serial data to parallel data on characters sent to or received from a peripheral device. The UART controller consists of a UART transmitter finite state machine (FSM), UART receiver FSM, and a baud rate generator.

UART Controller Block Diagram

Features

• Simple, easy-to-use UART with small logic utilization
• Configurable baud rates from 110 bps to 115.2 kbps
• Supports 8, 16, and 32 bit interfaces
• Supports an optional parity bit (even or odd parity for transmit and receive)
• Verilog RTL and simulation testbench
• Includes an example design targeting the Trion® T20 BGA256 Development Board and Titanium Ti60 F225 Development Board
• Supports all Trion and Titanium FPGAs