Titanium Ti35 FPGAs

Titanium Ti35 FPGAs

The Ti35 FPGA features the high-density, low-power 16 nm Efinix® Quantum™ fabric wrapped with an I/O interface in a small footprint package for easy integration. Ti35 FPGAs support mobile, edge, AI IoT, and sensor fusion markets that need low power, a small footprint, and a multitude of I/Os. Ti35 FPGAs:

  • Are fabricated on a 16 nm process.
  • Have high-voltage I/O (HVIO)—Simple I/O blocks that support the single-ended LVTTL and LVCMOS I/O standards.
  • Have high-speed I/O (HSIO)—Complex I/O blocks that support single-ended and differential I/O; LVDS, subLVDS, Mini-LVDS, and RSDS (RX, TX, and bidirectional) up to 1.6 Gbps; and also operate as MIPI lanes at 1.5 Gbps.
  • Have device configuration options including a standard SPI and JTAG interfaces.
  • Are fully supported by the Efinity® software, an RTL-to-bitstream compile.


Mobile, Consumer, IoT, Edge


Logic elements: 36176
XLR cells: 35467
10K RAM (bits): 1.53
10K RAM (blocks): 149
DSP Blocks: 93


Ti35 Data Sheet

Titanium Overview

Titanium FPGA 製品概要

Titanium Selector Guide

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Available Ti35 FPGAs

Package Pins HVIO HSIO PLLs Temp.
Where to Buy
Total as Pairs (1) as MIPI RX Lanes
Ti35F100S3F2C3 FBGA 100 0 61 30 21/3 3 C 3 Find distributor
Ti35F100S3F2C4 FBGA 100 0 61 30 21/3 3 C 4 Find distributor
Ti35F100S3F2I4 FBGA 100 0 61 30 21/3 3 I 4 Find distributor
Ti35F225C3 FBGA 225 23 140 70 58/12 4 C 3 Find distributor
Ti35F225C4 FBGA 225 23 140 70 58/12 4 C 4 Find distributor
Ti35F225I4 FBGA 225 23 140 70 58/12 4 I 4 Find distributor

1. You can use HSIO pairs as LVDS, differential HSTL, SSTL, or MIPI TX data and clock lanes.

Available Packages


F100 block diagram
(5.5 x 5.5 mm, 0.5 pitch)

F225 block diagram
(8 x 8 mm, 0.5 pitch)

Dimensions and blocks shown for illustrative purposes.