Titanium Ti60 FPGAs
The Ti60 FPGA features the high-density, low-power 16 nm Efinix® Quantum™ fabric wrapped with an I/O interface in a small footprint package for easy integration. Ti60 FPGAs support mobile, edge, AI IoT, and sensor fusion markets that need low power, a small footprint, and a multitude of I/Os. Ti60 FPGAs:
- Are fabricated on a 16 nm process.
- Have high-voltage I/O (HVIO)—Simple I/O blocks that support the single-ended LVTTL and LVCMOS I/O standards.
- Have high-speed I/O (HSIO)—Complex I/O blocks that support single-ended and differential I/O; LVDS, subLVDS, Mini-LVDS, and RSDS (RX, TX, and bidirectional) up to 1.6 Gbps; and also operate as MIPI lanes at 1.5 Gbps.
- Have device configuration options including a standard SPI and JTAG interfaces.
- Are fully supported by the Efinity® software, an RTL-to-bitstream compile.
Mobile, Consumer, IoT, Edge
Available Ti60 FPGAs
|Where to Buy|
|Total||as Pairs (1)||as MIPI RX Lanes
1. You can use HSIO pairs as LVDS, differential HSTL, SSTL, or MIPI TX data and clock lanes.
(3.5 x 3.4 mm, 0.4 pitch)
(5.5 x 5.5 mm, 0.5 pitch)
(8 x 8 mm, 0.5 pitch)