The DDR Hard Memory Controller-Calibration and Reset core helps you optimize timing and calibrate the DDR controller using write leveling, read leveling, gate training, and reset sequencing (memory initialization). The core supports an automated calibration mode as well as calibration on demand, depending on your configuration.

DDR Hard Memory Controller-Calibration and Reset Block Diagram

Features

• Automatically performs leveling calibration for the DDR DRAM interface and external memory module
• Supports write leveling, read leveling, reset (memory initialization), and gate training calibration
• x16 and x32 DQ widths
• Verilog RTL and simulation testbench
• Includes an example design targeting the T120 BGA324 development board
• Supports Trion FPGAs with DDR blocks