Powering Embedded Computing


SoC Based on the Open-Source RISC-V ISA

RISC-V is an open-source standard instruction set architecture (ISA) that is managed by the non-profit RISC-V Foundation. This modular ISA has a base instruction set and optional extension sets. Because RISC-V is free and open-source, it has gained popularity worldwide. Over 65 RISC-V cores, both commercial and open-source, are available today.

RISC-V logo

Sapphire SoC

Sapphire SoCEfinix has created RISC-V SoCs based on the VexRiscv core created by Charles Papon. The VexRiscv core, which won first place in the RISC-V SoftCPU contest in 2018, is a 32-bit CPU using the ISA RISCV32I with extensions, pipeline stages, and a configurable feature set. The SoC has a RISC-V processor, memory, a range of I/O, and interfaces for embedding user functions. You can easily create entire systems that include embedded compute and user-defined accelerators all in the same Titanium or Trion® FPGA.

The Sapphire SoC is a user-configurable, high-performance SoC with an optional memory controller. You can choose which peripherals you want by configuring the SoC in the Efinity IP Manager. This flexibility makes the Sapphire SoC ideal for a wide range of embedded applications. the Sapphire SoC is included with the Efinity IP Manager v2021.1 and higher.

  • 1 - 4 (user selectable) VexRiscv processor(s) with 6 pipeline stages (fetch, injector, decode, execute, memory, and write back), interrupts and exception handling with machine mode
  • 20 - 400 MHz system clock frequency
  • 1 - 512 KB on-chip RAM with boot loader for SPI flash
  • Memory controller for DDR or HyperRAM memories
    • Supports memory module sizes from 4 MB to 3.5 GB
    • User-configurable external memory bus frequency
    • 1 half duplex AXI3 interface (up to a 256-bit) to communicate with the external memory
    • 400 MHz DDR clock frequency, 800 Mbps
    • 200 MHz HyperRAM clock frequency, 400 Mbps
  • Up to 2 AXI master channels for user logic
  • 1 AXI slave channel to user logic
  • Includes a floating point unit

Included with the Efinity IP Manager v2021.1 and higher

  • Includes an optional Linux memory management unit
  • Includes a custom instruction interface with 1,024 IDs to perform different functions
  • Supports optional RISC-V extensions such as atomic and compressed
  • APB3 peripherals:
    • Up to 32 GPIOs
    • Up to 3 I2C masters
    • Clint timer
    • PLIC
    • Up to 3 SPI masters
    • Up to 3 user timers
    • Up to 3 UARTs with 115,200 baud rate
    • Up to 5 slave user peripherals
    • Up to 8 user interrupts

Sapphire SoC Block Diagram

Sapphire Multi-Core SoC Block Diagram

The Sapphire SoC incorporates a 32-bit RISC-V processor that has an instruction cache with up to 8 ways and a configurable size of 1 - 32 KB, a data cache with up to 8 ways and a configurable size of 1 - 32 KB, 4 - 512 KB of on-chip RAM, and a variety of peripherals (including 1 - 5 APB3 slave peripherals and 1 AXI slave). You can configure the operating frequency from 20 - 400 MHz (the actual performance is limited by the design's fMAX). The SoC includes 1 - 3 I2C peripherals, 1 - 3 UARTs, 1 - 3 user timers, and 1 - 3 SPI masters. The SoC also features a floating-point unit (FPU), custom instruction interface, and Linux memory management unit (MMU).

The default configuration has up to a 256-bit half-duplex AXI bus to communicate with the Efinix DDR controller or HyperRAM controller.

  • DDR controller—This core uses the Trion FPGAs hard DDR DRAM interface to reset an external DRAM module (resets and re-initializes the Trion FPGA's DDR interface as well as the DDR module(s)).
  • HyperRAM controller—This core controls HyperRAM memory modules.

You can customize the SoC using the IP Manager in the Efinity® software.

What's in the Package?

With each RISC-V SoC, Efinix provides a complete package of hardware and software files. Additionally, to help you develop software applications, Efinix distributes a collection of pre-compiled open-source software. With these packages, you can:

  • Build RTL designs using an example design targeting an Efinix development board, and learn how to extend the example for your own application.
  • Set up the software development environment using an example project, create your own software based on example projects, and use the provided API.

SoC Design Flow

SoC Design Flow


  • SoC RTL files
  • SoC testbench
  • Example design targeting an Efinix development board
  • Included with Efinity software


  • Board support package (BSP)
  • Linker script
  • SoC include header files
  • OpenOCD configuration files
  • Example software applications
  • Included with the Efinity software


  • Eclipse IDE for managing projects and software
  • GCC compiler
  • OpenOCD debugger for debugging
  • Windows build tools (Windows)
  • Download from the Support Center