Efinix® FPGAs have been widely adopted in a broad spectrum of applications from consumer electronics to edge compute, from AI image processing to industrial automation. They have a cost structure that can be used in high volume manufacturing, speeding time to market and eliminating financial and resource risks associated with designing custom ASICs. The FPGAs themselves are low power, making them a natural fit for demanding environmental conditions such as in surveillance or industrial automation applications.

But sometimes a standalone FPGA is not enough. Efinix's Reconfigurable Acceleration Platform (RAP) is an initiative that helps designers intuitively incorporate FPGAs in applications in which they can provide domain-specific compute and acceleration and adapt to changing workloads over the life of the product. RAP provides:

Hardware to balance time to market and costs for optimized solutions
Software to deliver a natural abstraction of hardware to speed time to market
Design flows to provide end-to-end support for mixed hardware/software systems

The RAP initiative lets you pick the technologies you need and assemble them in an easy-to-use package. You can start off using a standard off-the-shelf Trion or Trion Titanium FPGA. With chiplets, the first level of customization, you select components that best fit your application needs and combine them with an FPGA as a system-in-package (SIP). The result is a custom solution with lower cost and faster time to market. The next level is monolithic integration, in which you embed a standard FPGA core into your own SoC. These solutions are best for high volumes. Finally, when you need a completely custom solution, Efinix can help you design a Quantum® core to integrate into your ASIC. With RAP, you have a full range of solutions that can help you take your applications to the next level.

What does RAP include?

Under the RAP initiative, Efinix provides ready-to-use FPGAs as well as FPGAs in die form for integration into multi-chip modules. We can also incorporate your IP into custom FPGA devices and—by disassociating the core of the FPGA from its standard I/Os—can provide the underlying Quantum® fabric as a licensable core for inclusion in custom ASICs.

Level 1: Standalone FPGAs

Trion® and Trion Titanium FPGAs

Reconfigurable FPGA
Embedded hardened IP
Ready to use
Efinity® Design Suite support
Efinix soft IP ecosystem

Level 2: Multi-Chip SIPs

Trion, Trion Titanium, and Subsystems Chiplets

Known good die
SIP packaging for minimal size
Custom SIP configuration
Efinity® Design Suite support
Efinix soft IP ecosystem

Level 3: Domain Specific Silicon

Monolithic Integration of FPGA and Custom Subsystem

Customer subsystems integrated with Trion or Trion Titanium framework
Custom SoC configuration with Efinity® Design Suite support
Efinix soft IP ecosystem

Level 4: Quantum® Core Licensing

Monolithic Integration into Custom ASIC

Quantum® core in GDS
Core integration guidelines
Manufacturing test support
Efinity® Design Suite support
Efinix soft IP ecosystem

Complementing this enhanced hardware versatility, the RAP initiative also delivers an intuitive approach to system design and software partitioning. A standardized hardware accelerator interface lets you leverage the RISC-V cores available on Efinix FPGAs. You can build hardware accelerators in the FPGA, resulting in more intuitive hardware/software partitioning, reduced time to market, and dramatically improved system performance.

RAP Accelerator Flow

Solving Challenges at the Edge

With the global datasphere approaching 175 ZB by 2025, the need for devices to collect, capture, transform, transmit, and otherwise process all of this data is overwhelming. Devices now reside everywhere, potentially in harsh environments with limited access to power or consistent bandwidth. They need to process large quantities of data locally and securely in real time, only take up a small space, and consume very little power. These constraints are driving the need for innovative solutions. Adding to the problem, shrinking process geometries results in exponentially increasing costs. Designers cannot rely on the next-generation silicon to meet their time-to-market needs.

Applications at the edge are vast, chaotic, diverse, and evolving—and they need configurable, optimized solutions. By design, FPGAs are programmable, even after they are incorporated into a deployed product, which helps you adapt to changing requirements flexibly. At the edge, FPGAs can provide complete systems to solve real-world problems. The RAP initiative addresses two key problems for edge applications: the physical delivery mechanism and I/O diversity required in edge devices and the need to accelerate data processing within a framework of conventional software-driven applications and control structures.

Read white paper: Accelerating Edge Computing with Trion FPGAs

Watch Webinar Recording: Accelerating Edge Computing with FPGAs